High-bandwidth memory (HBM) gets discussed as a memory story, but its defining constraint is a packaging story: how do you stack eight, twelve, or sixteen DRAM dies, deliver clean power up through that stack, and evacuate the heat the stack traps — all while hitting terabyte-per-second bandwidth across the vertical connections? The June 2026 grant record lets you profile exactly where the IP behind those three problems sits, and it concentrates in two assignees.
Problem one — the stack itself. Intel Corporation's US12653065B2, "Semiconductor package with stacked memory devices" (issued 2026-06-09), is classified in G11C 5/06 (memory arrangement) alongside H10B 12/02 / 12/30 (DRAM device) and H10W packaging classes. That co-classification — memory + DRAM device + package — is the signature of a stacked-memory package claim: the patent is not about the DRAM cell or the package alone, but about the assembled stacked-memory module as a unit.
Problem two — power. Intel's US12653047B2, "Composite bridges for 3D stacked integrated circuit power delivery" (2026-06-09), addresses the part of the stack that is hardest to disclose cleanly: getting current up through a tall die stack without the IR-drop and inductance that kill high-speed memory. The "composite bridge" language and H10W 70/65 / 90/24 classifications point at a hybrid interconnect bridge dedicated to power, distinct from the signal interconnect. For an HBM stack, power-delivery IP is as load-bearing as the data path.
Problem three — heat. Samsung Electronics Co., Ltd.'s US12653043B2, "Semiconductor package including heat dissipation structure" (2026-06-09), classified in H10W 70/611 and H10W 70/685, claims the thermal path. This is not incidental: a sixteen-high stack is a thermal nightmare because the dies in the middle have nowhere to dump heat. Owning a heat-dissipation-structure claim in a stacked package is owning a piece of the constraint that currently caps stack height.
Profile the portfolio and the division of labor is clear. Intel's mid-2026 stacked-memory IP spans the assembly and its power delivery — consistent with a company that integrates memory into its own packaged products. Samsung's claim sits on thermal — consistent with a memory maker whose stacks must survive the field. The white space is the intersection: a power-and-thermal co-designed bridge structure is implied by neither claim's element list as filed in this batch.
The strategic read for a competitive-intelligence team: when an HBM roadmap promises a taller stack or higher bandwidth, the gating IP is rarely the DRAM cell. It is the package, the power bridge, and the thermal structure — and the June 2026 grants show two of the largest players have already begun fencing all three.