Semiconductor IP
As chips get wired from both sides, new failure modes appear — and so do new claims. IBM's June 2026 double-sided IC grant shows the electrostatic guard ring is the limitation doing the work.
Semiconductor IP
Compute density is now a heat problem, and heat is becoming patent territory. TSMC's liquid-cooled lid and Samsung's heat-dissipation grants show thermal IP moving onto the commercial critical path.
Semiconductor IP
The advanced-packaging boom has a paper trail older than the hype. Tracing a 2017 Micron interposer grant to the 2026 fan-out packages shows how early IP positions cash in.
Semiconductor IP
Memory density now scales up, not out. Two June 2026 grants show the split between vertically stacked transistor-storage cells (Micron) and a full monolithic 3D fabrication route (Monolithic 3D Inc.).
Semiconductor IP
Integrated fan-out is how TSMC turned packaging into a competitive moat. Three June 2026 grants — RDL design, package structure, and dielectric method — show a portfolio engineered for breadth.
Semiconductor IP
SRAM scaling is where logic-node bragging rights are won. A June 2026 TSMC grant on an SRAM middle strap with a feedthrough via shows how granular — and how routing-specific — leading-edge memory-cell IP has become.
Semiconductor IP
ASML builds the EUV scanner, but the patentable process around it is wide open. Two June 2026 grants — a pattern-formation method and a vacuum-bake step — show where foundries and tool makers actually claim scope.
Semiconductor IP
The chiplet era runs on die-to-die links. The interesting June 2026 grants are not from the foundries — they are from specialists claiming the bandwidth-balancing and connectivity-monitoring layers UCIe leaves open.
Semiconductor IP
HBM's bandwidth is a packaging achievement as much as a memory one. Intel and Samsung's June 2026 grants show where the stacking, power, and thermal IP actually concentrates.
Semiconductor IP
Hybrid bonding is the connective tissue of advanced packaging. The June 2026 grants show three assignees claiming three non-overlapping pieces — passive devices, barrier metallurgy, and the stacked-structure interface.
Semiconductor IP
Backside power is the headline; the backside contact is the limitation that matters. Two June 2026 grants show how narrowly — and how differently — each assignee claims the connection.
Semiconductor IP
Two foundries, two strategies, one transistor architecture. Reading the June 2026 nanosheet grants shows the thicket is built around buried power and parasitic control, not the channel itself.