If you want to understand the gate-all-around (GAA) thicket in 2026, stop looking at the nanosheet channel and start looking at everything bolted around it. The stacked horizontal sheets that define a GAA device are, by now, broadly disclosed prior art across every leading foundry. The patents that are still being granted — and therefore the territory still being contested — are about integrating that channel into a manufacturable, power-fed, low-parasitic cell. The June 2026 grant batch makes the map unusually legible.
Start with International Business Machines Corporation. Its grant US12652827B2, "Nanosheet transistors with buried power rails" (issued 2026-06-09), is classified in H10D 30/6713 and H10W 20/435 — note the H10W power-distribution classifications sitting alongside the H10D device classes. That co-classification is the tell: IBM is not claiming the nanosheet, it is claiming the nanosheet with the buried power rail as an integrated structure. The independent claim's value lives in that combination, not in either element alone.
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) approaches the same architecture from a different corner. Its grant US12652845B2, "Semiconductor structures with reduced parasitic capacitance and methods for forming the same" (2026-06-09), is dense with H10D 64 and H10D 30/6757 classifications — the inner-spacer and source/drain region detail where parasitic capacitance is won or lost in a nanosheet stack. TSMC is fencing the electrostatics, not the topology.
The third pin on the map is process. TSMC's US12648181B2, "Multiple gate patterning methods towards future nanosheet scaling" (issued 2026-06-02), claims the patterning sequence itself. This is a method patent, and it matters for thicket purposes precisely because a method claim can wall off a manufacturing route even when the resulting device looks generic. A competitor can design around a structure; designing around a patterning method is harder when your fab flow already depends on it.
Read the three together and the white space becomes visible. IBM is strong on buried-rail integration; TSMC is layered on parasitics and patterning. Neither cluster forecloses the other, which is why both can hold mid-2026 grants on the same transistor family. The unclaimed territory — and the place a fourth entrant would have to file — is in the backside-contact-to-buried-rail interface, where IBM's power-rail claims and TSMC's parasitic claims do not quite meet.
For an IP strategist, the practical read is this: GAA freedom-to-operate analysis should not start at "do we infringe the nanosheet?" — almost no one holds that anymore — but at "whose buried-power, parasitic, and patterning claims does our specific integration flow touch?" The thicket is in the integration, and the June 2026 record draws its boundaries cleanly.