Static random-access memory (SRAM) is the quiet battleground of leading-edge logic. SRAM bit-cell area is the number foundries cite to prove a node actually shrank, because SRAM scales worse than logic — so every fractional improvement in the cell's internal wiring is worth patenting. Taiwan Semiconductor Manufacturing Company, Ltd.'s June 2026 grant is a clean example of how granular that IP has become.
US12653015B2, "SRAM middle strap with feedthrough via" (issued 2026-06-09), is classified in H10B 10/125 (SRAM device structure) plus H01L 23/5226 and 23/5283 (interconnect/routing layers). Construe the title as the claim's spine: a "middle strap" is a conductive tie placed in the middle of the cell layout, and a "feedthrough via" is a vertical connection that passes through a layer to reach it. The limitation that matters is the combination — a strap located in a specified region of the cell, connected by a via that feeds through an intervening layer. This is not a claim on SRAM; it is a claim on one routing topology inside the cell.
Why does such a narrow structure merit a grant and a fight? Because in a sub-3nm SRAM cell, routing congestion — not transistor count — sets the area. The internal nodes of a six-transistor cell must be tied together in a footprint that keeps shrinking, and a strap-plus-feedthrough that frees up a track is a real area win. Owning that specific topology means a competitor who lands on the same congestion solution infringes; one who routes the tie differently does not. The design-around is a different strap location or a different via stack — feasible, but it costs the area advantage the patent captures.
The companion grant, US12652859B2, "Standard cells with multi-well size placements" (2026-06-09; CPC H10D 89/10, H10D 84/85), fences a different cell-level lever: placing wells of different sizes within the standard-cell framework. Construe this as a layout/placement claim — the limitation is the relationship between differently sized wells and the cell boundary, not any single transistor. Layout-rule patents like this are subtle in scope because they read on a design-rule choice an EDA flow makes automatically; infringement can be inadvertent.
Reading the two together shows TSMC's SRAM/standard-cell strategy as a routing-and-placement thicket rather than a device thicket. Neither claims a transistor; both claim how the cell is wired and laid out. For a freedom-to-operate review, that means the risk is not in your transistor architecture but in your cell-layout and routing choices — exactly the things a competitor's place-and-route flow produces by default.
The construction takeaway: leading-edge SRAM IP has descended to the level of individual straps, vias, and well placements. "We use a standard 6T SRAM" clears nothing; the question is whether your specific cell layout recites the claimed middle-strap-plus-feedthrough geometry, and that is answerable only by overlaying your cell on the independent claim element by element.